The present invention relates to a vertical semiconductor structure, applicable to semiconductor devices such as MOSFET""s (insulated gate field effect transistors), IGBT""s (insulated gate bipolar transistors), bipolar transistors and diodes, that facilitates realizing a high breakdown voltage and a high current capacity. The present invention relates also to a semiconductor device including such a vertical semiconductor structure and the method of manufacturing such a semiconductor device.
The semiconductor devices may be roughly classified into a lateral semiconductor device that arranges its electrodes on a major surface and a vertical semiconductor device that distributes its electrodes on both major surfaces facing opposite to each other. When the vertical semiconductor device is ON, a drift current flows in the thickness direction of the semiconductor chip (vertical direction). When the vertical semiconductor device is OFF, the depletion layers caused by applying a reverse bias voltage expand also in the vertical direction. FIG. 51 is a cross sectional view of a conventional planar-type n-channel MOSFET.
Referring now to FIG. 51, the vertical MOSFET includes an n+-type drain layer 51 with low electrical resistance, a drain electrode 58 in electrical contact with n+-type drain layer 51, a highly resistive n-type drift layer 52 on n+-type drain layer 51, p-type base regions 53 formed selectively in the surface portion of n-type drift layer 52, a heavily doped n+-type source regions 54 formed selectively in p-type base regions 53, a gate insulation film 55 on the extended portion of p-type base regions 53 extended between n+-type source region 54 and n-type drift layer 52, a gate electrode layer 56 on gate insulation film 55, and a source electrode 57 in contact commonly with n+-type source regions 54 and p-type base regions 53.
In the vertical semiconductor device shown in FIG. 51, highly resistive n-type drift layer 52 works as a region for making a drift current flow vertically when the MOSFET is in the ON-state. In the OFF-state of the MOSFET, n-type drift layer 52 is depleted to obtain a high breakdown voltage. Shortening the current path in highly resistive n-type drift layer 52 is effective for substantially reducing the on-resistance (resistance between the drain and the source) of the MOSFET, since the drift resistance is lowered in the ON-state of the device. However, the short current path in n-type drift layer 52 lowers the breakdown voltage (the voltage between the drain D and the source S), since the width between the drain D and the source S, for that the depletion layers expand from the pn-junctions between p-type base regions 53 and n-type drift layer 52, is narrowed and the electric field strength in the depletion layers soon reaches the maximum (critical) value for silicon.
However, in the semiconductor device with a high breakdown voltage, a thick n-type drift layer 2 inevitably causes high on-resistance and loss increase. Thus, the breakdown voltage or the on-resistance is improved at the sacrifice of the on-resistance or the breakdown voltage. In short, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the MOSFET. The tradeoff relation exists in the other semiconductor devices such as IGBT""s, bipolar transistors and diodes. The tradeoff relation exists also in lateral semiconductor devices, in that the flow direction of the drift current in the ON-state of the devices is different from the expansion direction of the depletion layers expanded by a reverse bias voltage applied in the OFF-state of the devices.
European Patent 0 053 854, U.S. Pat. Nos. 5,216,275, 5,438,215, and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose semiconductor devices include an alternating conductivity type drift layer formed of heavily doped n-type regions and p-type regions alternately laminated with each other. The alternating conductivity type drift layer is depleted to bear the breakdown voltage in the OFF-state of the device.
FIG. 52 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to FIG. 52, the vertical MOSFET of FIG. 52 is different from the vertical MOSFET of FIG. 51 in that the vertical MOSFET of FIG. 52 includes a drift layer 62, that is not a single-layered one but formed of n-type first semiconductor regions 62a and p-type second semiconductor regions 62b alternately laminated with each other. In the figure, p-type well regions 63, n+-type source regions 64, gate insulation films 65, gate electrode layers 66, a source electrode 67, and a drain electrode 68 are shown.
The drift layer 62 is formed in the following way. A highly resistive n-type layer is epitaxially grown on an n+-type drain layer 61 used as a substrate. Trenches are dug through the n-type layer down to n+-type drain layer 61 by selective etching, leaving n-type first semiconductor regions 62a. Then, p-type second semiconductor regions 62b are formed by epitaxially growing p-type layers in the trenches.
Thus, the vertical semiconductor device shown in FIG. 52, in that a current flows between the electrodes arranged on two major surfaces facing opposite to each other, has a laminate-type drift layer of alternating conductivity types formed of first semiconductor regions of a first conductivity type, that provide a current path in the ON-state of the semiconductor device and are depleted in the OFF-state of the semiconductor device, and second semiconductor regions of a second conductivity types.
Hereinafter, the semiconductor device including an alternating conductivity type drift layer will be referred to as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
In the super-junction semiconductor device, the tradeoff relation between the on-resistance RONA and the breakdown voltage VB is expressed theoretically by the following relational expression (1).
RONA=(4dVB)(xcexcOxcex5SEC2)xe2x80x83xe2x80x83(1)
Here, xcexc is the electron mobility, xcex5O the dielectric permeability of the vacuum, xcex5S the relative dielectric permeability of silicon, d the width of the n-type drift region, and EC the critical electric field strength.
As the relational expression (1) indicates, the on-resistance of the super-junction semiconductor device increases merely in proportion to the breakdown voltage. When the breakdown voltage is raised, the on-resistance is not increased so greatly. The on-resistance is reduced, at a fixed breakdown voltage, by narrowing the n-type first semiconductor regions.
A method of manufacturing a super-junction semiconductor device with an excellent mass-productivity is disclosed in Japanese Unexamined Laid Open Patent Application 2000-40822. According to the method disclosed in the above identified patent application, at least first semiconductor regions of the first conductivity type or second semiconductor regions of the second conductivity type are formed through one or more steps of epitaxial growth, one or more steps of ion implantation and one or more steps of heat treatment.
According to the method described above, however, an alternating conductivity type layer is formed by repeating the steps of epitaxial growth, ion implantation and heat treatment, and, then, the electrode means of the MOSFET are formed on the side of the first major surface and on the side of the second major surface. Since it is difficult for the method described above to conduct formation of the alternating conductivity type layer and to conduct formation of the device structure on the sides of the major surfaces individually, manufacturing steps are increased and complicated, causing manufacturing costs increase. Since it is indispensable to conduct heat treatment for forming the device structure on the side of the first major surface, the alternating conductivity type layer subjects to increasing times of heat treatment and, therefore, ideal characteristics for the alternating conductivity type layer are not obtained.
Corresponding to thickening the alternating conductivity type layer for obtaining a higher breakdown voltage, heat treatment is conducted more times, causing the problems described above more seriously. Therefore, the method described above has a certain limit for realizing a higher breakdown voltage.
In view of the foregoing, it is an object of the invention to provide a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. It is another object of the invention to provide the method that facilitates manufacturing the super-junction semiconductor device with reduced costs and with an excellent mass-productivity without increasing times of heat treatment of the alternating conductivity type layer subjects, and without impairing the characteristics of the alternating conductivity type layer.
According to a first aspect of the invention, there is provided a method of manufacturing a super-junction semiconductor device, the semiconductor device including a semiconductor chip having a first major surface, a second major surface facing opposite to the first major surface, a device structure in the first major surface, and an alternating conductivity type layer between the first major surface and the second major surface, the alternating conductivity type layer being formed of first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type, the first semiconductor regions and the second semiconductor regions being arranged alternately with each other, the method including the steps of: forming at least a part of the first semiconductor regions or the second semiconductor regions from the side of the second major surface. The planar arrangement of the first semiconductor regions and the second semiconductor regions may be a stripe arrangement, a lattice arrangement or a net arrangement.
The manufacturing method according to the invention facilitates forming the alternating conductivity type layer and the surface device structure separately, simplifying the manufacturing steps reducing the heat cycles, thereto the alternating conductivity type layer subjects, and preventing the characteristics of alternating conductivity type layer from being impaired. Since the device structure such as a surface MOSFET structure is formed first on the side of the first major surface and, then, trenches are formed and the trenches are buried from the side of the second major surface (the back surface), the alternating conductivity type layer does not subject to excessive heat cycles and ideal pn-junctions are obtained. The method according to the invention facilitates manufacturing a semiconductor device, that greatly reduces the tradeoff relation between the breakdown voltage and the on-resistance, with reduced manufacturing costs and with an excellent mass-productivity.
Advantageously, the device structure includes a MIS structure, a pn-junction or a Schottky junction.
Advantageously, the method further includes the step of forming at least a part of the device structure prior to the steps of forming at least a part of the first semiconductor regions or the second semiconductor regions from the side of the second major surface. The manufacturing step order described above facilitates reducing the heat cycles, thereto the alternating conductivity type layer subjects.
Advantageously, the steps of forming at least a part of the first semiconductor regions or the second semiconductor regions from the side of the second major surface include the step of forming trenches by selective etching and the step of burying the trenches by epitaxial growth. By employing selective etching for forming trenches and epitaxial growth for burying the trenches, the alternating conductivity type layer is formed easily from the side of the second major surface.
Preferably, the epitaxial growth is selective epitaxial growth or liquid phase epitaxial growth. The selective epitaxial growth or the liquid phase epitaxial growth facilitates obtaining an almost uniform and continuous impurity distribution in the depth direction as compared with the combination of epitaxial growth, ion implantation and heat treatment.
Preferably, the selective etching is anisotropic etching. The anisotropic etching facilitates easy formation of the trenches.
Advantageously, the steps of forming at least a part of the first semiconductor regions or the second semiconductor regions from the side of the second major surface include the step of selectively implanting impurity ions or repeating the step of selectively implanting and the step of heat treatment. This step combination, that introduces an impurity element by ion implantation, makes it unnecessary to form trenches and to bury the trenches, and greatly reduces the manufacturing steps. If the surface MOSFET is formed on the side of the first major surface, it will be enough to conduct minimum heat treatments for activating the implanted ions, since the ions are implanted from the side of the second major surface. Although a wave-shaped impurity distribution is caused, deviation of the impurity distribution is not caused in the depth direction.
Advantageously, the method further includes the step of polishing the semiconductor chip mechanically or chemically, prior to or after forming the alternating conductivity type layer, from the side of the second major surface so that the alternating conductivity type layer may have a predetermined thickness from the first major surface. Since it is necessary to adjust the thickness of the alternating conductivity type layer considering the designed breakdown voltage class, the polishing step is very effective to adjust the thickness of the alternating conductivity type layer easily. If the semiconductor chip is adjusted at a desired thickness prior to forming the alternating conductivity type layer, the manufacturing efficiency will be improved.
Preferably, the first semiconductor regions or the second semiconductor regions are formed on the side of the second major surface by implanting impurity ions of the first conductivity type or the second conductivity type and thermally treating the ions. The combination of the ion implantation and the subsequent heat treatment facilitates forming a necessary electrode on the second major surface.
Preferably, the impurity concentration in the first semiconductor regions or the second semiconductor regions is 1xc3x971018 cm3 or higher. When the impurity concentration in said regions is 1xc3x971018 cm3 or higher, a satisfactory ohmic contact with the electrode on the second major surface is obtained.
According to a second aspect of the invention, there is provided a method of manufacturing a super-junction semiconductor device including an alternating conductivity type layer, the semiconductor device including a first semiconductor chip having a first major surface, and a device structure in the first major surface, and a second semiconductor chip having at least a part of the alternating conductivity type layer, the alternating conductivity type layer being formed of first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type, the first semiconductor regions and the second semiconductor regions being arranged alternately with each other, the method including the step of: connecting the first semiconductor chip and the second semiconductor chip with each other.
According to this manufacturing method, the semiconductor chip having the first major surface and the semiconductor chip having at least a part of the alternating conductivity type layer are manufactured separately, the heat cycles, thereto the alternating conductivity type layer subjects, are reduced, and an ideal alternating conductivity type layer is obtained.
Advantageously, the second semiconductor chip has a second major surface facing opposite to the first major surface, and a second main electrode on the second major surface.
Advantageously, the step of connecting includes the step of bonding the first semiconductor chip and the second semiconductor chip with each other.
Advantageously, the semiconductor device further includes a third semiconductor chip having at least another part of the alternating conductivity type layer, and the method includes the step of bonding the first semiconductor chip and the third semiconductor chip, and the step of bonding the third semiconductor chip and the second semiconductor chip.
Preferably, the bonding portions of the semiconductor chips are polished, oxide films are removed and the bonding steps are conducted at a predetermined temperature.
The super-junction semiconductor device including a plurality of semiconductor chips bonded with each other facilitates adjusting the thickness of the alternating conductivity type layer and, therefore, obtaining a desired breakdown voltage.
Advantageously, the first semiconductor regions or the second semiconductor regions are buried by epitaxial growth in the trenches formed by selective etching. Preferably, the epitaxial growth is selective epitaxial growth or liquid phase epitaxial growth. Preferably, the selective etching is anisotropic etching.
Advantageously, at least a part of the first semiconductor regions or at least a part of the second semiconductor regions is formed by selectively implanting impurity ions of the first conductivity type or the second conductivity type one or more times and thermally treating the ions.
Advantageously, the bottom face of each of the trenches is a (110) plane or a (100) plane of silicon and the side face of each of the trenches is a (111) plane of silicon.
Since silicon crystal grows faster in the [110] direction or in the [100] direction than in the [111] direction, the trenches are buried without causing any void even when the aspect ratio of the trenches is large.
According to a third aspect of the invention, there is provided a semiconductor device including: a semiconductor chip; the semiconductor chip including a first major surface; a second major surface facing opposite to the first major surface; an alternating conductivity type layer between the first major surface and the second major surface, the alternating conductivity type layer being formed of drift regions of a first conductivity type and second semiconductor regions of a second conductivity type, the first semiconductor regions and the second semiconductor regions being alternately arranged with each other, at least a part of the first semiconductor regions or a part of the second semiconductor regions being formed from the side of the second major surface; well regions of the second conductivity type on the side of the first major surface; source regions of the first conductivity type, the source regions being separated from the first semiconductor regions by the well regions; gate electrodes above the surfaces of the well regions contacting with the source regions with respective gate insulation films interposed between the gate electrodes and the surfaces of the well regions; the well regions being shaped with respective stripes extending in parallel with a first spacing left therebetween; and the second semiconductor regions being shaped with respective stripes extending in parallel with a second spacing left therebetween.
According to a fourth aspect of the invention, there is provided a super-junction semiconductor device including an alternating conductivity type layer, the alternating conductivity type layer including first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type, the first semiconductor regions and the second semiconductor regions being alternately arranged with each other, the semiconductor device including: a first semiconductor chip including a first major surface a second semiconductor chip including a second major surface facing opposite to the first major surface, a second main electrode on the second major surface, and at least a part of the alternating conductivity type layer; a connecting portion between the first semiconductor chip and the second semiconductor chip; the first semiconductor chip including well regions of the second conductivity type on the side of the first major surface, source regions of the first conductivity type, the source regions being separated from the first semiconductor regions by the well regions, and gate electrodes above the surfaces of the well regions contacting with the source regions with respective gate insulation films interposed between the gate electrodes and the surfaces of the well regions; the well regions being shaped with respective stripes extending in parallel with a first spacing left therebetween; and the second semiconductor regions being shaped with respective stripes extending in parallel with a second spacing left therebetween.
Advantageously, the bonding portion is a bonding plane or a third semiconductor chip including at least another part of the alternating conductivity type layer.
Advantageously, the semiconductor device further includes surface drain regions of the first conductivity type between the well regions, the surface drain regions including a portion, the net impurity concentration thereof being higher than the impurity concentration in the first semiconductor regions.
Advantageously, the first semiconductor regions are shaped with respective stripes extending in parallel to each other with a certain spacing left therebetween.
Advantageously, the gate electrodes are shaped with respective stripes extending in parallel to each other with a certain spacing left therebetween.
Advantageously, the extending direction of the stripes of the well regions and the extending direction of the stripes of the second semiconductor regions are different from each other. Preferably, the stripes of the well regions and the stripes of the second semiconductor regions extend in perpendicular to each other.
Since the surface JFET effect is reduced as far as the net impurity concentrations are high in a portion of the surface drain region, the configurations described above facilitate reducing the on-resistance. When the stripes of the well regions and the stripes of the second semiconductor regions are almost perpendicular to each other, it is not necessary to precisely position the surface MOSFET structure and the alternating conductivity type layer with each other, and, therefore, a semiconductor device exhibiting an excellent performance is manufactured easily.